1. Field of the Invention
This invention relates to generation of clock signals and more particularly to generating clock signals using phase-locked loops with interpolative dividers.
2. Description of the Related Art
High speed, high port density networking applications require multiple jitter attenuating phase-locked loops (PLLs). Markets for such devices include the 10 Gigabit, 40 Gigabit, and 100 Gigabit telecom/datacom infrastructure. However, putting multiple PLLs on a single integrated circuit can result in a large silicon area being utilized, particularly if the PLLs utilize LC voltage controlled oscillators. In addition, LC oscillators with close frequencies can have cross talk problems.